A New Dft Architecture to Reduce Test Data Volume and Test Application Time

نویسندگان

  • Zhang Ling
  • Mei Junjin
چکیده

Article history: Received: 28.11.2014. Received in revised form: 5.3.2015. Accepted: 7.3.2015. This paper proposes a new DFT Architecture that contains three test scan modes. The test data could be interval broadcast to scan chains whenever the data in corresponding locations are compatible. Compared with the conventional broadcast scan architecture, the proposed architecture achieves better compression ratio in all cases, and the test application time is also induced. The hardware overhead is very low. Both theoretical and experimental results prove efficacy and versatility of the proposed scheme.

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

H-DFT: A Hybrid DFT Architecture For Low-Cost High Quality Structural Testing

This paper describes a Hybrid DFT (H-DFT) architecture for low-cost, high quality structural testing in the high volume manufacturing (HVM) environment. This structure efficiently combines several testing and test data compression approaches to enable application of a huge amount of ATPG and Weighed Random-BIST (WR-BIST) patterns. Results obtained from the application of the H-DFT technique to ...

متن کامل

Reducing Test Power, Time and Data Volume in SoC Testing Using Selective Trigger Scan Architecture

Time, power and data volume are among the most challenging problems in test of System-onChip (SoC) devices. These problems become even more important in scan-based test. The Selective Trigger Scan architecture introduced in this paper addresses these problems. This architecture reduces switching activity in circuit-under-test (CUT) and increases the scan clock frequency. Format of data for this...

متن کامل

Digital Circuits Testing Based on Pattern Overlapping and Broadcasting

and contributions The high test data volume and long test application time are two major concerns for testing scan based circuits. Broadcast-based test compression techniques can reduce both the test data volume and test application time. Pattern overlapping test compression techniques are proven to be highly effective in the test data volume reduction. This dissertation thesis presents a new t...

متن کامل

Techniques to Reduce Data Volume and Application Time for Transition Test

Scan based transition tests are added to improve the detection of speed failures using scan tests. Empirical data suggests that both data volume and application time, for transition test, will increase dramatically. Techniques to address the above problem, for a class of transition tests called “enhanced transition tests”, are proposed. The first technique, which combines the ATE repeat capabil...

متن کامل

Multiple Scan Chains for Power Minimization during Test Application in Sequential Circuits

This paper presents a new technique for power minimization during test application in sequential circuits using multiple scan chains. The technique is based on a new design for test (DFT) architecture and a novel test application strategy which reduces spurious transitions in the circuit under test. To facilitate the reduction of spurious transitions, the proposed DFT architecture is based on c...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

عنوان ژورنال:

دوره   شماره 

صفحات  -

تاریخ انتشار 2016